This application claims the priority benefit of Taiwan application serial no. Sep. 9, 2003, filed 92124834.
1. Field of the Invention
The present invention relates to a method of forming a semiconductor device. More particularly, the present invention relates to a method of forming bit lines and bit line contacts of a dynamic random access memory.
2. Description of the Related Art
Memory is a semiconductor device for holding data or parameters. In a digital device, memory capacity is often expressed in term of the number of bits that can be held. Each memory unit for storing a single bit of data is called a memory cell. In general, the memory cells are organized into a memory array with the address of each memory cell specified through the intersection of a particular row and column. The memory cells in a row or a column is serially connected together via a common conductive wire. A dynamic random access memory is a memory device that utilizes the charged or uncharged state of a capacitor to store a bit of binary data. Each capacitor is capable of representing a single bit of memory data. Typically, a fully charged capacitor represents the storage of a binary bit xe2x80x9c1xe2x80x9d and a fully discharged capacitor represents the storage of a binary bit xe2x80x9c0xe2x80x9d. Similarly, the memory cells in a dynamic random access memory are connected serially together through a common conductive wire. All the serially connected memory cells in a row (or a column) is referred to as a word line and the conductive wires related to the transmission of data is called bit lines.
FIG. 1 is a schematic cross-sectional view showing a bit line and bit line contact of a conventional dynamic random access memory. As shown in FIG. 1, a conventional memory device comprises substrate 100 with a plurality of gate structures 108 thereon. Each gate structure 108 comprises a gate dielectric layer 102, a gate conductive layer 104 and a cap layer 106. Furthermore, spacers 110 are formed on the sidewalls of the gate structures 108. A dielectric layer 112 is also formed over the substrate 100 covering the gate structures 108. The dielectric layer 112 has a bit line contact 114 therein. In general, a self-aligned contact process is performed to fabricate the bit line contact 114. A bit line 116 is also formed over the dielectric layer 112 such that the bit line 116 and the bit line contact 114 are electrically connected.
Since a self-aligned contact process is used to form the bit line contact 114 of a conventional memory device, the top surface area of the bit line contact 114 is quite large.
FIG. 2 is a top view of the structure shown in FIG. 1. As shown in FIG. 2, the bit lines 116 cross over the gate structures 108 and the bit line contact 114 is located underneath the bit line 116 between two adjacent gate structures 108. Because the bit line contact 114 has a larger dimension, the distance xe2x80x9caxe2x80x9d between the bit line contact 114 and the bit line 116 is smaller than the distance xe2x80x9cbxe2x80x9d between the two bit lines 116. If there is a slight shift in the pattern layout due to processing variation, the probability of having a short circuit between the bit line contact 114 and adjacent bit line 116 is increased.
Accordingly, one object of the present invention is to provide a method of forming bit lines and bit line contacts of a memory device in a manner to prevent a possible short-circuit between a bit line contact and an adjacent bit line.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming bit lines and bit line contacts of a memory device. First, a substrate having a plurality of gate structures formed thereon is provided. Each gate structure further comprises a gate dielectric layer, a gate conductive layer and a cap layer. Furthermore, spacers are formed on the sidewalls of each gate structures. Thereafter, a barrier layer is formed over the substrate to cover the gate structures. The barrier layer between two adjacent gate structures is removed to expose a portion of the substrate. A conductive layer is deposited over the substrate to cover the gate structures. The conductive layer is fabricated using doped polysilicon material, for example. Thereafter, a chemical mechanical polishing is performed to planarize the conductive layer until the cap layer of the gate structures is exposed. A portion of the conductive layer is removed so that the conductive layer between the two adjacent gate structures is retained to form a bit line contact. A dielectric layer is formed over the substrate to cover the gate structures. The dielectric layer is planarized to expose cap layer of the gate structures. A stop layer is formed over the substrate to cover the dielectric layer and the gate structures but exposes the bit line contact. A first dielectric layer is formed over the stop layer and then a trench is formed within the first dielectric layer to expose the bit line contact. A conductive material is deposited into the trench to form a bit line. The bit line and the bit line contacts are electrically connected such that the bit line contact has a width almost identical to the bit line.
This invention also provides a method of forming a memory device. First, a substrate having a memory cell region and a peripheral circuit region is provided. Thereafter, a plurality of gate structures is formed in the memory cell region. Each gate structure comprises a gate dielectric layer, a gate conductive layer and a cap layer. Spacers are formed on the sidewalls of the gate structures. A barrier layer is formed over the substrate to cover the gate structures. The barrier layer between two adjacent gate structures is removed to expose a portion of the substrate. A conductive layer is deposited over the substrate to cover the gate structures. The conductive layer is fabricated using doped polysilicon material, for example. Thereafter, a chemical mechanical polishing is performed to planarize the conductive layer until the cap layer of the gate structures is exposed. A portion of the conductive layer is removed so that the conductive layer between the two adjacent gate structures is retained to form a bit line contact. A dielectric layer is formed over the substrate to cover the gate structures. The dielectric layer is planarized to expose cap layer of the gate structures. A stopping layer is formed over the substrate to cover the dielectric layer and the gate structures but exposes the bit line contact. A first dielectric layer is formed over the stopping layer and then a trench is formed within the first dielectric layer to expose the bit line contact. An opening is formed in the dielectric layer within the peripheral circuit region to expose a portion of the substrate. A conductive material is deposited into the trench to form a bit line and a contact. The bit line is electrically connected to the bit line contact within the memory cell region and the contact within the peripheral circuit region such that the bit line contact has a width almost identical to the bit line.
Since the dimension of the bit line contact in this invention is smaller than a bit line contact formed by a conventional method, the probability of having a short circuit between a bit line contact and its adjacent bit line is greatly reduced.
Furthermore, forming a stopping layer underneath the bit line ensures the thickness of the bit line above the memory device is uniform.
In addition, the contact openings in the peripheral circuit region are defined at the bottom of the trench after the trench is formed. Hence, the contact openings can be easily formed because of a lower aspect ratio.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.